In the production of microelectronic products, transistors are typically formed on a substrate and interconnected into integrated circuits that perform numerous useful functions. In some applications, multi-gate non-planar transistors, such as double gate or floating body cell (FBC) transistors, may be employed. In the fabrication of multi-gate transistors, a fin provides the channel region of the transistor. In double gate or FBC transistors, the fin typically includes a silicon element that provides the channel material of the transistor and an insulative cap over the silicon element.
FIGS. 1A-1D illustrate prior art methods of forming a fin for a multi-gate non-planar transistor. FIG. 1A illustrates a silicon on insulator (SOI) substrate 100 including a bulk silicon layer 105, an insulator layer 110, and a silicon layer 115. FIG. 1A also illustrates an oxide layer 120, a nitride layer 125, a hard mask layer 130, and a resist pattern 135.
As illustrated in FIG. 1B, an optional trim step may be performed to trim resist pattern 135 to resist pattern 140. Typically, resist pattern 140 has smaller critical dimensions than resist pattern 135.
As illustrated in FIG. 1C, an etch is typically performed to remove portions of hard mask layer 130 and nitride layer 125 that are not covered by resist pattern 135 to form a patterned hard mask layer 145 and a patterned nitride layer 150. Hard mask layer 130 and nitride layer 125 are typically etched with similar chemistries without an inherent etch selectivity between them.
The etch process that removes portions of nitride layer 125 and hard mask layer 130 has numerous difficulties. For example, as shown, resist pattern 140 is partially consumed during the etch process. The consumption of resist pattern 140 may cause poor profile control in patterned hard mask layer 145 and/or patterned nitride layer 150, and may cause a trapezoidal patterned hard mask layer 145 and/or nitride layer 145 as shown in FIG. 1C. Patterned hard mask layer 145 and patterned nitride layer 150 may also include undesired line edge roughness and poor critical dimension (CD) control. Further, in an effort to make transistors smaller and faster, critical dimensions must be reduced. However, the illustrated method limits the aspect ratio and critical dimension of patterned nitride layer 150 and therefore limits the desired scaling to smaller transistors.
As illustrated in FIG. 1D, resist pattern 140 may be removed, and portions of oxide layer 120 and silicon layer 115 may be removed to form pattered oxide layer 155 and patterned silicon layer 160. Patterned silicon layer 160, pattered oxide layer 155, patterned carbon doped nitride 150, and, optionally, patterned hard mask layer 145 make up a fin 160 that is used to form a multi-gate non-planar transistor by known methods.